ASIC Verification Engineer

Job Description

<p><strong><span >WE'RE HIRING!</span></strong></p><p><span >At HTG, you’ll push boundaries with the latest tech and collaborate with a team that loves what they do. Be part of a design services company that is amongst the companies that lead the world in technology and innovation.</span></p><p><strong><span >Your next chapter starts here. </span></strong></p><p><span > </span></p><p><span >Your responsibilities include:</span></p><ul><li><p><span >Read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.</span></p></li><li><p><span >Thoroughly validate one or more architectural functional blocks using a combination of simulation, formal, and coverage methods.</span></p></li><li><p><span >Develop verification, functional coverage and formal verification test plans.</span></p></li><li><p><span >Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and/or C.</span></p></li><li><p><span >Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function's designer.</span></p></li><li><p><span >Provide regular status updates on verification progress on a regular basis.</span> </p></li></ul><p> </p>